Currently, there are a variety of applications in which it is desirable to determine the time of an event signal with respect to a reference signal. For instance, devices, such as time interval analyzers, time interval digitizers, timing discriminators, time interval counters, etc. (collectively referred to herein as “time interval analyzers”) are typically used to measure the time difference between two asynchronous events. Such devices, as well as others, typically implement a time stamping circuit to determine the time of each particular event to be measured with respect to a reference signal. In this regard, the time stamping circuit may be viewed as generating a time stamp corresponding to each particular event to be measured. Thus, the time difference between the occurrence of two events may be measured by comparing the time stamp of one event to the time stamp of another.
There are a variety of existing time stamping techniques for determining the time of a particular event with respect to a reference signal. One common technique involves: (1) generating a pulse that begins with the event to be measured and ends with the reference signal; (2) converting the pulse to an analog voltage; and (3) measuring and converting the analog voltage into a digital value. FIG. 1 illustrates a schematic diagram of an existing system 102 that employs this technique. As illustrated in FIG. 1, system 102 includes a time stamping circuit 104, a ramp generator 110, an analog-digital converter (ADC) 112, and a digital signal processor (DSP) 114.
Typically, time stamping circuit 104 consists of a memory logic circuit 106 (e.g., a flip-flop, latch, other sequential logic circuit(s), etc.) having a data input for receiving an event signal (for which a time stamp is to be generated), an enable input for receiving a clock signal (CLOCK0), and an output terminal for providing an output signal (OUTPUT0). As known in the art, in sequential logic circuits, the output of the sequential circuit is a function of the current inputs and any signals that are fed back to the inputs. The so-called feedback signals may be referred to as the current state of the sequential logic circuit. Typically, a periodic external event (e.g., a clock) determines when the sequential logic circuit will change the current state to a new state. When the clocking event occurs, the sequential logic circuit samples the current inputs and the current state and determines a new, or next, state.
As further illustrated in FIG. 1, the output of memory logic circuit 106 and the original event signal are provided to a logic circuit, logic device, logic gate, etc. (e.g., “XOR” gate 108), which generates a pulse signal (PULSE0). As stated above, the pulse signal (PULSE0) begins with the event to be measured (i.e., the event signal) and ends with the reference signal (i.e., CLOCK0). Referring again to FIG. 1, after the pulse signal (PULSE0) is generated, it may be provided to ramp generator 110. As know in the art, ramp generator 110 converts the pulse signal (PULSE0) into a corresponding voltage (Voltage (PULSE0)). For example, ramp generator 110 may use the pulse signal (PULSE0) to enable a current source that charges a capacitor for the duration of the pulse signal (PULSE0), resulting in a voltage on the capacitor that is directly proportional to the length of the pulse signal (PULSE0). Then, the voltage on the capacitor may be converted by ADC 112 and/or processed by DSP 114.
FIG. 2 is a timing diagram of the various relevant signals within time stamping circuit 104 that further illustrates its general operation. As illustrated in FIG. 2, the output signal (OUTPUT0) of memory logic 106 is a function of the clock signal (CLOCK0) and the event signal. For instance, where memory logic circuit 106 is implemented using a positive edge-triggered D flip-flop, each next state of the output signal (OUTPUT0) is determined at the rising edge of the clock signal (CLOCK0) based on the current state of the output signal (OUTPUT0) and the current state of the event signal. Consider the situation in which an event to be time stamped occurs at time tE. Referring to FIG. 1, the current state of the output signal (OUTPUT0)—logic zero—will be changed to a next state—logic one—at the next rising edge of the clock signal (CLOCK0) at time tC. The pulse signal (PULSE0) may be generated by performing a logical XOR operation based on the event signal and the output signal (OUTPUT0). As illustrated in FIG. 2, the resulting pulse signal (PULSE0) begins at time tE and ends at time tC.
The time resolution provided by existing time stamping techniques, however, may be very limiting. In existing approaches, the resolution of the time stamp measurement is limited by the resolution of the ADC and, to a greater extent, the maximum frequency that the sequential logic (e.g., flip-flops) can be clocked. For example, because the time stamp measurement is directly proportional to the width of the pulse signal (i.e., tC−tE), the time resolution is limited by the period of the clock. In other words, the resolution of the time stamp measurement is defined by the maximum possible time between the occurrence of the event (tE) and the next possible clock triggering event (i.e., positive clock edge or negative clock edge) at tC. In such systems, the resolution may be calculated as the maximum pulse width divided by 2n for an n-bit analog-to-digital converter. Using existing techniques, the resolution may be the clock period divided by 2n for an ideal circuit.
Thus, there is a need in the industry for systems, methods, and circuits for improving the resolution of time stamping techniques.